Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 24)

2–16 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Arria II GX FPGA Development Board, 6G Edition Reference Manual © July 2010 Altera Corporation
FPGA Programming over External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
(U19) using an external USB-Blaster device with the Quartus II Programmer running
on a PC. The external USB-Blaster is connected to the board through the JTAG
connector (J5). Install a shunt onto the JTAG chain header (J9) pins 1 and 2 to remove
the MAX II CPLD device from the JTAG chain so that the FPGA is the only device on
the JTAG chain.
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For more information on the following topics, refer to the respective documents:
■ Board Update Portal, refer to the Arria II GX FPGA Development Kit, 6G Edition User
Guide .
■ PFL design, refer to the Arria II GX FPGA Development Kit, 6G Edition User Guide .
■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.
Status Elements
The development board includes status LEDs. This section describes the status
elements.
Table 2–10 lists the LED board references, names, and functional descriptions.
Table 2–9. Load Image Push-Button Switch (PB5) LED Settings (1) (2)
IMAGE0 IMAGE1 IMAGE2 Design
ON OFF OFF Factory hardware
OFF ON OFF User hardware 1
OFF OFF ON User hardware 2
Notes to Table 2–9 :
(1) ON indicates a setting of ’1’.
(2) OFF indicates a setting of ’0’.
Table 2–10. Board-Specific LEDs (Part 1 of 2)
Board Reference LED Name Description
D18 Power Blue LED. Illuminates when 2.5 V power is active.
D14 CONF DONE Green LED. Illuminates when the FPGA is successfully configured. Driven by the
MAX II CPLD EPM2210 System Controller.
D15 Loading Green LED. Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA. Driven by the MAX II CPLD EPM2210 System
Controller wire-OR'd with the embedded USB-Blaster CPLD.
D16 Error Red LED. Illuminates when the MAX II CPLD EPM2210 System Controller fails to
configure the FPGA. Driven by the MAX II CPLD EPM2210 System Controller.
D11, D12, D13 CONFIG[2:0] Green LEDs. Illuminates to indicate which hardware page loads from flash
memory.
D19 ENET TX Green LED. Illuminates to indicate Ethernet PHY transmit activity. Driven by the
Marvell 88E1111 PHY.
D20 ENET RX Green LED. Illuminates to indicate Ethernet PHY receive activity. Driven by the
Marvell 88E1111 PHY.