Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 53)

Chapter 2: Board Components 2–45
Memory
© July 2010 Altera Corporation Arria II GX FPGA Development Board, 6G Edition Reference Manual
Table 2–43. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board Reference Description Schematic Signal Name I/O Standard
Arria II GX Device
Pin Number
U22.R6 Address bus FSM_A2
2.5-V
D29
U22.P6 Address bus FSM_A3 J21
U22.A2 Address bus FSM_A4 L13
U22.A10 Address bus FSM_A5 C8
U22.B2 Address bus FSM_A6 N9
U22.B10 Address bus FSM_A7 D20
U22.N6 Address bus FSM_A8 A23
U22.P3 Address bus FSM_A9 B24
U22.P4 Address bus FSM_A10 C24
U22.P8 Address bus FSM_A11 E25
U22.P9 Address bus FSM_A12 F21
U22.P10 Address bus FSM_A13 J19
U22.P11 Address bus FSM_A14 H19
U22.R3 Address bus FSM_A15 K21
U22.R4 Address bus FSM_A16 L21
U22.R8 Address bus FSM_A17 F25
U22.R9 Address bus FSM_A18 F26
U22.R10 Address bus FSM_A19 G23
U22.R11 Address bus FSM_A20 H21
U22.B1 Address bus FSM_A21 M13
U22.A1 Address bus FSM_A22 P7
U22.J10 Data bus FSM_D0 A19
U22.J11 Data bus FSM_D1 C18
U22.K10 Data bus FSM_D2 D28
U22.K11 Data bus FSM_D3 B19
U22.L10 Data bus FSM_D4 E19
U22.L11 Data bus FSM_D5 E18
U22.M10 Data bus FSM_D6 G19
U22.M11 Data bus FSM_D7 F19
U22.D10 Data bus FSM_D8 D21
U22.D11 Data bus FSM_D9 D23
U22.E10 Data bus FSM_D10 D24
U22.E11 Data bus FSM_D11 A25
U22.F10 Data bus FSM_D12 B25
U22.F11 Data bus FSM_D13 A26
U22.G10 Data bus FSM_D14 C26
U22.G11 Data bus FSM_D15 A27
U22.D1 Data bus FSM_D16 R9