Memory, Ddr3, Memory –38 – Altera Arria II GX FPGA Development Board, 6G Edition User Manual
Page 46: Ddr3 –38
2–38
Chapter 2: Board Components
Memory
Arria II GX FPGA Development Board, 6G Edition Reference Manual
© July 2010 Altera Corporation
lists the HSMC connector component reference and manufacturing
information.
Memory
This section describes the board's memory interface support and also their signal
names, types, and connectivity relative to the Arria II GX device. The board has the
following memory interfaces:
■
DDR3
■
DDR2 SODIMM
■
SSRAM
■
Flash
f
For more information about the memory interfaces, refer to the following documents:
■
section in volume 4 of the External Memory Interface Handbook.
■
section in volume 6 of the
External Memory Interf
DDR3
There is a single DDR3 device, providing 128-Mbyte interface with a 16-bit data bus.
This memory interface is designed to run at a maximum frequency of 333 MHz for a
maximum theoretical bandwidth of over 10.6 Gbps. The internal bus in the FPGA is
typically 2 or 4 times the width at full-rate or half-rate respectively. For example, a
333 MHz 16-bit interface will become a 166.5 MHz 64-bit bus.
lists the DDR3 pin assignments, signal names, and functions. The signal
names and types are relative to the Arria II device in terms of I/O setting and
direction.
J1.158
Dedicated CMOS I/O bit 75
HSMB_D75
2.5-V
V5
J1.160
HSMC port B presence detect
HSMB_PSNT_n
AG28
D2
User LED to show RX data activity on
HSMC port B
HSMB_RX_LED
AF23
D3
User LED to show TX data activity on HSMC
port B
HSMB_TX_LED
AE24
Table 2–37. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board
Reference
Description
Schematic Signal
Name
I/O Standard
Arria II GX
Device
Pin Number
Table 2–38. HSMC Connector Component Reference and Manufacturing Information
Board Reference
Description
Manufacturer
Manufacturing
Part Number
Manufacturer
Website
J1 and J2
HSMC, custom version of QSH-DP
family high-speed socket.
Samtec
ASP-122953-01