Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 39)

Chapter 2: Board Components 2–31
Components and Interfaces
© July 2010 Altera Corporation Arria II GX FPGA Development Board, 6G Edition Reference Manual
Table 2–35 lists the Ethernet PHY interface component reference and manufacturing
information.
High-Speed Mezzanine Cards
The development board contains two HSMC interfaces called port A and port B. The
HSMC port B is only available in the Arria II GX FPGA development board, 6G
Edition. HSMC port A interface supports both single-ended and differential signaling
while HSMC port B interface only supports single-ended signaling. The HSMC
interface also allows JTAG, SMB, clock outputs and inputs, as well as power for
compatible HSMC cards. The HSMC is an Altera-developed open specification, which
allows you to expand the functionality of the development board through the
addition of daughtercards (HSMCs).
f
For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, and mechanical information, refer to the
High
Speed Mezzanine Card (HSMC) Specification manual.
The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series.
Figure 2–10 shows the bank arrangement of signals with respect to the Samtec
connector's three banks.
Table 2–35. Ethernet PHY Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U24 Ethernet PHY BASE-T device Marvell
Semiconductor 88E1111-B2-CAAIC000 www.marvell.com
Figure 2–10. HSMC Signal and Bank Diagram
Bank 3
Power
D(79.40)
-or-
LVDS
CLKIN2, CLKOUT2
Bank 2
Power
D(39:0)
-or-
D[3:0] + LVDS
CLKIN1, CLKOUT1
Bank 1
8 TX Channels CDR
8 RX Channels CDR
JTAG
SMB
CLKIN0, CLKOUT0