Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 21)

Chapter 2: Board Components 2–13
Configuration, Status, and Setup Elements
© July 2010 Altera Corporation Arria II GX FPGA Development Board, 6G Edition Reference Manual
The default method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash memory over the network.
The secondary method is to use the pre-built parallel flash loader (PFL) design
included in the development kit. The development board implements the Altera PFL
megafunction for flash memory programming. The PFL megafunction is a block of
logic that is programmed into an Altera programmable logic device (FPGA or CPLD).
The PFL functions as a utility for writing to a compatible flash memory device. This
pre-built design contains the PFL megafunction that allows you to write either page 0,
page 1, or other areas of flash memory over the USB interface using the Quartus II
software. This method is used to restore the development board to its factory default
settings.
Other methods to program the flash memory can be used as well, including the
Nios
® II processor.
f For more information on the Nios II processor, refer to the Nios II Processor page of
the Altera website.
FPGA Programming from Flash Memory
On either power-up or by pressing the load image push-button switch (PB5), the
MAX
II CPLD EPM2210 System Controller's PFL configures the FPGA from the flash
memory when the CONFIG_LED0 is ON. The PFL megafunction reads 16-bit data
from the flash memory and converts it to fast passive parallel (FPP) format. This 8-bit
data is then written to the FPGA's dedicated configuration pins during configuration.