Figure 17: jtag tap controller state machine – Altera Virtual JTAG IP Core User Manual
Page 36
Figure 17: JTAG TAP Controller State Machine
CAPTURE_DR
SHIFT_DR
EXIT1_DR
PAUSE_DR
EXIT2_DR
UPDATE_DR
CAPTURE_IR
SHIFT_IR
EXIT1_IR
PAUSE_IR
EXIT2_IR
UPDATE_IR
RUN_TEST/
IDLE
TEST_LOGIC/
RESET
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
TMS = 0
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 0
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 0
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
TMS = 0
TMS = 0
TMS = 0
TMS = 1
SELECT_
DR_SCAN
SELECT_
IR_SCAN
Table 15: Functional Description for the TAP Controller States
Functional Description
TAP Controller State
The test logic of the JTAG scan chain is disabled.
Test-Logic-Reset
Virtual JTAG Megafunction (sld_virtual_jtag)
Altera Corporation
UG-SLDVRTL
Design Example: TAP Controller State Machine
36
2014.03.19
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