Altera Virtual JTAG IP Core - Manual (Page 19)

To use the Tcl API to query for the bit pattern in your design, use the
show_equivalent_device_ir_dr_shift
argument with the
device_virtual_ir_shift
and
device_virtual_dr_shift
commands.
Both examples are from the same design, with a single Virtual JTAG instance. The VIR length for the reference
Virtual JTAG instance is configured to 3 bits in length.
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values
VIR shifts consist of a
USER1
(
0x0E
) IR shift followed by a DR shift to the virtual Instruction Register. The
DR Scan shift consists of the value passed by the - dr_value argument. The length and value of the DR shift
is dependent on the number of SLD nodes in your design. This value consists of address bits to the SLD
node instance concatenated with the desired value of the virtual Instruction Register. The addressing scheme
is determined by the Quartus II software during design compilation.
The Tcl command examples below show a VIR/VDR transaction with the
no_captured_value
option set.
The commands return the underlying JTAG shift transactions that occur.
Virtual IR Shift with the no_captured_value Option
device_virtual_ir_shift -instance_index 0 -ir_value 1 \
-no_captured_ir_value -show_equivalent_device_ir_dr_shift
Returns:
Info: Equivalent device ir and dr shift commands
Info: device_ir_shift -ir_value 14
Info: device_dr_shift -length 5 -dr_value 11 -value_in_hex
Virtual DR Shift with the no_captured_value Option
device_virtual_dr_shift -instance_index 0 -length 8 -dr_value \
04 -value_in_hex -no_captured_dr_value \
-show_equivalent_device_ir_dr_shift
Returns:
Info: Equivalent device ir and dr shift commands
Info: device_ir_shift -ir_value 12
Info: device_dr_shift -length 8 -dr_value 04 -value_in_hex
The VIR value field in the figure below is four bits long, even though the VIR length is configured to be three
bits long, and shows the bit values and fields associated with the VIR/VDR scans. The Instruction Register
length for all Altera FPGAs and CPLDs is 10-bits long. The
USER1
value is
0x0E
and
USER0
value is
0x0C
for
all Altera FPGAs and CPLDs. The Address bits contained in the DR scan shift of a VIR scan are determined
by the Quartus II software.
All
USER1
DR chains must be of uniform length. The length of the VIR value field length is determined by
length of the longest VIR register for all SLD nodes instantiated in the design. Because the SLD hub VIR is
Altera Corporation Virtual JTAG Megafunction (sld_virtual_jtag)
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19 Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values
UG-SLDVRTL
2014.03.19