Altera Virtual JTAG IP Core - Manual (Page 2)

Examples of debugging applications include induced trigger conditions evaluated by a SignalTap ® II Logic
Analyzer by exercising test signals connected to the analyzer instance, a replacement for a front panel interface
during the prototyping phase of the design, or inserted test vectors for exercising the design under test.
The SLD infrastructure is an extension of the JTAG protocol for use with Altera-specific applications and
user applications, such as the SignalTap II Logic Analyzer.
Device Family Support
The Virtual JTAG megafunction supports the following Altera device families:
• Arria ® series
• Stratix ® series
• Cyclone ® series
• HardCopy ® series
• APEX ™ II, APEX 20KE, APEX 20KC
On-Chip Debugging Tool Suite
The On-Chip Debugging Tool Suite enables real time verification of a design and includes the following
tools:
Table 1: On-Chip Debugging Tool Suite
Typical Circumstances for Use Description Tool
You have spare on-chip memory
and want functional verification
of your design running in
hardware. Uses FPGA resources to sample tests
nodes and outputs the information to
the Quartus II software for display
and analysis. SignalTap II Logic Analyzer
You have spare I/O pins and want
to check the operation of a small
set of control pins using either an
external logic analyzer or an
oscilloscope. Incrementally routes internal signals
to I/O pins while preserving the
results from your last place-and-
route. SignalProbe
You have limited on-chip memory
and have a large set of internal
data buses that you want to verify
using an external logic analyzer.
Logic analyzer vendors, such as
Tektronics and Agilent, provide
integration with the tool to
improve usability. Multiplexes a larger set of signals to
a smaller number of spare I/O pins.
LAI allows you to select which signals
are switched onto the I/O pins over a
JTAG connection. Logic Analyzer Interface (LAI)
Virtual JTAG Megafunction (sld_virtual_jtag) Altera Corporation
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Device Family Support 2
2014.03.19