Altera Virtual JTAG IP Core - Manual (Page 34)

jtag_state_cir,
jtag_state_e1dr,
jtag_state_e1ir,
jtag_state_e2dr,
jtag_state_e2ir,
jtag_state_pdr,
jtag_state_pir,
jtag_state_rti,
jtag_state_sdr,
jtag_state_sdrs,
jtag_state_sir,
jtag_state_sirs,
jtag_state_tlr,
jtag_state_udr,
jtag_state_uir,
tck,
tdi,
tms,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir
);
VHDL Component Declaration
The following VHDL component declaration is located in the ALTERA_MF_COMPONENTS.vhd file
located in the <Quartus II installation directory>\libraries\vhdl\altera_mf directory.
component sld_virtual_jtag
generic (
lpm_hint : string := "UNUSED";
lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1;
sld_sim_action : string := "UNUSED";
sld_sim_n_scan : natural := 0;
sld_sim_total_length : natural := 0 );
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out: in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
Virtual JTAG Megafunction (sld_virtual_jtag) Altera Corporation
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VHDL Component Declaration 34
2014.03.19