Altera Virtual JTAG IP Core - Manual (Page 35)

jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
VHDL LIBRARY-USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
Design Example: TAP Controller State Machine
The TAP controller is a state machine with a set of control signals that routes TDI data between the Instruction
Register and the bank of DR chains. It controls the start and stop of any shift transactions, and controls the
data flow between the parallel hold registers and the shift registers of the Instruction Register and the Data
Register. The TAP controller is controlled by the
TMS
pin.
The figure below shows the TAP controller state machine. The table that follows provides a description of
each of the states.
Altera Corporation Virtual JTAG Megafunction (sld_virtual_jtag)
Send Feedback
35 VHDL LIBRARY-USE Declaration
UG-SLDVRTL
2014.03.19