Altera Virtual JTAG IP Core User Manual

Page 24

• The

ir_in

output port of the Virtual JTAG megafunction is the parallel output of the contents that get

shifted into the virtual IR of the Virtual JTAG instance. This port is used for decoding logic to select the
active virtual DR chain.

The purpose of instantiating a Virtual JTAG instance in this example is to load

my_counter

through the

JTAG port using a software application built with Tcl commands and the

quartus_stp

executable. In this

design, the Virtual JTAG instance is called

my_vji

. Whenever a Virtual JTAG megafunction is instantiated

in a design, three logic blocks are usually needed: a decode logic block, a

TDO

logic block, and a Data Register

block. The example below combines the Virtual JTAG instance, the decode logic, the

TDO

logic and the Data

You can use the following Verilog HDL template as a guide for instantiating and connecting various signals
of the megafunctions in your design.

module counter (clock, my_counter);
input clock;
output [3:0] my_counter;
reg [3:0] my_counter;
always @ (posedge clock)
if (load && e1dr) // decode logic: used to load the counter my_counter
my_counter <= tmp_reg;
else
my_counter <= my_counter + 1;
// Signals and registers declared for VJI instance
wire tck, tdi;
reg tdo;
wire cdr, eldr, e2dr, pdr, sdr, udr, uir, cir;
wire [1:0] ir_in;

// Instantiation of VJI
my_vji VJI_INST(
.tdo (tdo),
.tck (tck),
.tdi (tdi),
.tms(),
.ir_in(ir_in),
.ir_out(),
.virtual_state_cdr (cdr),
.virtual_state_e1dr(e1dr),
.virtual_state_e2dr(e2dr),
.virtual_state_pdr (pdr),
.virtual_state_sdr (sdr),
.virtual_state_udr (udr),
.virtual_state_uir (uir),
.virtual_state_cir (cir)
);
// Declaration of data register
reg [3:0] tmp_reg;
// Deocde Logic Block
// Making some decode logic from ir_in output port of VJI
wire load = ir_in[1] && ~ir_in[0];
// Bypass used to maintain the scan chain continuity for
// tdi and tdo ports

bypass_reg <= tdi;
// Data Register Block
always @ (posedge tck)
if ( load && sdr )
tmp_reg <= {tdi, tmp_reg[3:1]};
// tdo Logic Block
always @ (tmp_reg[0] or bypass_reg)
if(load)
tdo <= tmp_reg[0]

Virtual JTAG Megafunction (sld_virtual_jtag)

Altera Corporation

Send Feedback

UG-SLDVRTL

Instantiating the Virtual JTAG Megafunction in Your Design

2014.03.19