Altera FIR Compiler II MegaCore Function User Manual
Page 8
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Parameters
ALM
DSP
Blocks
Memory
Registers
f
MAX
(MHz)
Channel
Wires
Filter Type
Coefficients
M10K M20K Primary Secondary
8
1
Interpolation —
381
5
0
—
442
32
27
8
8
1
Interpolation Write
514
5
0
—
540
27
27
8
8
1
Single Rate
—
493
10
0
—
191
20
27
8
8
1
Single Rate
Write
633
10
0
—
588
1
27
8
1
—
Decimation
—
220
3
0
—
158
27
31
0
1 super
sample
—
Decimation
—
404
20
0
—
400
41
30
5
1 super
sample
—
Decimation
Write
505
20
0
—
785
35
30
8
1
—
Decimation
Write
318
3
0
—
208
26
30
9
1 Half
Band
—
Decimation
—
234
3
0
—
192
34
30
8
1 Half
Band
—
Decimation
Write
320
3
0
—
232
27
30
9
1
—
Fractional
Rate
—
297
3
0
—
504
57
31
0
1
—
Fractional
Rate
Write
391
3
0
—
563
56
31
0
1 Half
Band
—
Fractional
Rate
—
196
2
0
—
251
5
27
7
1 Half
Band
—
Fractional
Rate
Write
266
2
0
—
301
15
28
0
1
—
Interpolation —
266
5
0
—
290
30
27
8
1 super
sample
—
Interpolation —
717
32
0
—
903
45
30
8
1 super
sample
—
Interpolation Write
842
32
0
—
1,281
48
30
8
1
—
Interpolation Write
405
5
0
—
380
15
27
8
UG-01072
2014.12.15
FIR II IP Core Performance and Resource Utilization
1-5
About the FIR II IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)