Altera FIR Compiler II MegaCore Function User Manual
Page 14
Parameters
ALM
DSP
Blocks
Memory
Registers
f
MAX
(MHz)
Channel
Wires
Filter Type
Coefficients
M10K M20K Primary Secondary
1 Half
Band
—
Decimation
—
226
3
—
0
206
16
45
0
1 Half
Band
—
Decimation
Write
343
3
—
0
327
18
45
0
1
—
Fractional
Rate
—
252
3
—
0
318
21
44
5
1
—
Fractional
Rate
Write
353
3
—
0
380
13
45
0
1 Half
Band
—
Fractional
Rate
—
140
2
—
0
185
13
45
0
1 Half
Band
—
Fractional
Rate
Write
214
2
—
0
235
21
45
0
1
—
Interpolation —
168
5
—
0
127
19
45
0
1 super
sample
—
Interpolation —
573
32
—
0
1,084
51
44
6
1 super
sample
—
Interpolation Write
870
32
—
0
1,774
136
45
0
1
—
Interpolation Write
313
5
—
0
196
5
45
0
1 Half
Band
—
Interpolation —
253
3
—
0
292
9
45
0
1 Half
Band
—
Interpolation Write
370
4
—
0
418
9
45
0
1
—
Single rate
—
226
10
—
0
706
31
44
7
1 _
ssample
—
Single rate
—
468
20
—
0
1,354
53
45
0
1 _
ssample
—
Single rate
Write
927
20
—
0
2,267
203
45
0
1
—
Single rate
Write
524
10
—
0
1,391
31
50
0
1 Half
Band
—
Single rate
—
195
5
—
0
270
50
45
0
1 Half
Band
—
Single rate
Write
351
5
—
0
645
28
45
0
UG-01072
2014.12.15
FIR II IP Core Performance and Resource Utilization
1-11
About the FIR II IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)