Altera FIR Compiler II MegaCore Function User Manual
Page 11
![background image](https://www.manualsdir.com/files/763723/content/doc011.png)
Parameters
ALM
DSP
Blocks
Memory
Registers
f
MAX
(MHz)
Channel
Wires
Filter Type
Coefficients
M10K M20K Primary Secondary
1
—
Decimation
—
219
3
0
—
159
23
28
9
1 super
sample
—
Decimation
—
404
20
0
—
398
43
28
8
1 super
sample
—
Decimation
Write
503
20
0
—
774
46
25
6
1
—
Decimation
Write
312
3
0
—
208
26
28
9
1 Half
Band
—
Decimation
—
234
3
0
—
192
29
28
9
1 Half
Band
—
Decimation
Write
323
3
0
—
228
32
28
8
1
—
Fractional
Rate
—
422
3
0
—
723
94
31
0
1
—
Fractional
Rate
Write
516
3
0
—
787
86
29
2
1 Half
Band
—
Fractional
Rate
—
195
2
0
—
251
12
26
1
1 Half
Band
—
Fractional
Rate
Write
267
2
0
—
299
15
25
2
1
—
Interpolation —
262
5
0
—
296
25
25
2
1 super
sample
—
Interpolation —
708
32
0
—
914
34
27
2
1 super
sample
—
Interpolation Write
841
32
0
—
1,297
32
25
9
1
—
Interpolation Write
400
5
0
—
382
12
25
8
1 Half
Band
—
Interpolation —
288
3
0
—
456
13
29
0
1 Half
Band
—
Interpolation Write
331
4
0
—
315
9
29
0
1
—
Single rate
—
87
10
0
—
142
14
25
3
1 super
sample
—
Single rate
—
258
20
0
—
315
33
26
0
1-8
FIR II IP Core Performance and Resource Utilization
UG-01072
2014.12.15
Altera Corporation
About the FIR II IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)