Altera FIR Compiler II MegaCore Function User Manual
Page 13

Parameters
ALM
DSP
Blocks
Memory
Registers
f
MAX
(MHz)
Channel
Wires
Filter Type
Coefficients
M10K M20K Primary Secondary
8
2
Interpolation Multiple
banks;
Write
2,652 32
—
0
2,842
236
42
4
8
2
Single rate
—
920
20
—
0
332
2
44
4
8
2
Single rate
Write
1,359 20
—
0
1,323
1
45
0
8
1
Decimation
—
340
3
—
0
324
25
45
0
8
1
Decimation
Write
463
3
—
0
457
29
45
0
8
1
Decimation
Multiple
banks
466
3
—
0
569
42
45
0
8
1
Decimation
Multiple
banks;
Write
577
3
—
0
567
41
45
0
8
1
Fractional
Rate
—
709
5
—
0
870
45
45
0
8
1
Fractional
Rate
Write
852
5
—
0
991
65
45
0
8
1
Interpolation —
216
5
—
0
197
13
45
0
8
1
Interpolation Write
361
5
—
0
290
22
45
0
8
1
Single Rate
—
483
10
—
0
212
4
44
7
8
1
Single Rate
Write
783
10
—
0
894
4
45
0
1
—
Decimation
—
215
3
—
0
175
10
45
0
1 super
sample
—
Decimation
—
547
20
—
0
1,167
88
45
0
1 super
sample
—
Decimation
Write
989
20
—
0
2,214
105
45
0
1
—
Decimation
Write
331
3
—
0
310
7
45
0
1-10
FIR II IP Core Performance and Resource Utilization
UG-01072
2014.12.15
Altera Corporation
About the FIR II IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)