Super sample rate – Altera FIR Compiler II MegaCore Function User Manual
Page 52
Figure 4-25: Correct Input Format (11 valid cycles, 11 invalid cycles)
clk
areset
xin_v[0]
xin_c[7:0]
xin_0[7:0]
xin_1[7:0]
xout_v[0]
xout_c[7:0]
xout_0[17:0]
xout_1[17:0]
xout_2[17:0]
xout_3[17:0]
xout_4[17:0]
xout_5[17:0]
xout_6[17:0]
xout_7[17:0]
xout_8[17:0]
xout_9[17:0]
xout_10[17:0]
1
0
1
2
3
4
5
6
7
8
9
10
11
4
1
2
3
4
5
6
13
14
15
16
17
18
19
20
21
22
15
12
13
14
15
16
17
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
8
16
6
12
0
3FFF9
24
32
18
24
0
3FFEB
40
48
30
36
0
3FFDD
56
64
42
48
0
3FFCF
72
80
54
60
0
3FFC1
88
96
66
72
0
3FFB3
104
112
78
84
0
3FFA5
120
128
90
96
0
3FF97
136
144
102
108
0
3FF89
152
160
114
120
0
3FF7B
168
176
126
132
0
3FF6D
1
12
You can insert extra invalid cycles at the end, which mean the number of invalid cycles can be greater
than 9, but they must not interrupt the packets of data after the process has started.
Super Sample Rate
For a “super sample rate” filter the sample rate is greater than the clock rate. In this example, clock rate =
100, sample rate = 200, inputChannelNum = 1, and single rate. The optimization produces a filter with
PhysChanIn = 2, ChansPerPhyIn = 1, PhysChanOut = 2, and ChansPerPhyOut = 1.
Figure 4-26: Super Sample Rate Filter (clkRate=100, inputRate=200) with inChans=1A0 is the first
sample of channel A, A1 is the second sample of channel A, and so forth.
clk
xln_v
xln_0
xln_1
xOut_v
xOut_c
xOut_0
xOut_1
A0
A2
A4
A6
A8
A10
A12
A14
A16
A18
A20
A22
A24
A26
A28
A1
A3
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A0
A2
A4
A6
A8
A10
A12
A14
A1
A3
A5
A7
A9
A11
A13
A15
00
00
UG-01072
2014.12.15
Super Sample Rate
4-19
FIR II IP Core Functional Description
Altera Corporation