Altera FIR Compiler II MegaCore Function - Manual (Page 27)

Parameter Value Description
Clock Frequency
(MHz)
1–500 Specifies the frequency of the input clock.
Clock Slack Integer Enables you to control the amount of pipelining
independently of the clock frequency and
therefore independently of the clock to sample
rate ratio.
Input Sample Rate
(MSPS)
Integer Specifies the sample rate of the incoming data.
Coefficient Options
Coefficient Scaling
Auto
None Specifies the coefficient scaling mode. Select Auto
to apply a scaling factor in which the maximum
coefficient value equals the maximum possible
value for a given number of bits. Select None to
read in pre-scaled integer values for the
coefficients and disable scaling.
Coefficient Data
Type
Signed Binary
Signed Fractional Binary Specifies the coefficient input data type. Select
Signed Fractional Binary to monitor which bits
are preserved and which bits are removed during
the filtering process.
Coefficient Bit
Width
2–32 Specifies the width of the coefficients. The default
value is 8 bits.
Coefficient
Fractional Bit Width
0–32 Specifies the width of the coefficient data input
into the filter when you select Signed Fractional
Binary as your coefficient data type.
Coefficients Reload Options
Coefficients Reload —
Turn on this option to allow coefficient reloading.
This option allows you to change coefficient
values during run time. When this option is
turned on, additional input ports are added to the
filter.
Base Address Integer Specifies the base address of the memory-mapped
coefficients.
Read/Write mode Read
Write
Read/Write Specifies the read and write mode that determines
the type of address decode to build.
Flow Control
3-2 Filter Specification Parameters
UG-01072
2014.12.15
Altera Corporation FIR II IP Core Parameters
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