Altera FIR Compiler II MegaCore Function User Manual
Page 10

Parameters
ALM
DSP
Blocks
Memory
Registers
f
MAX
(MHz)
Channel
Wires
Filter Type
Coefficients
M10K M20K Primary Secondary
8
2
Fractional
Rate
Write
2,301 16
0
—
3,601
476
25
0
8
2
Interpolation —
1,840 32
0
—
2,431
48
25
5
8
2
Interpolation Write
1,988 32
0
—
2,813
57
25
2
8
2
Interpolation Multiple
banks
2,006 32
0
—
2,711
98
25
3
8
2
Interpolation Multiple
banks;
Write
2,704 32
0
—
2,990
100
25
0
8
2
Single rate
—
934
20
0
—
317
19
25
2
8
2
Single rate
Write
1,053 20
0
—
704
12
25
1
8
1
Decimation
—
474
3
1
—
541
50
27
5
8
1
Decimation
Write
559
3
1
—
574
58
27
3
8
1
Decimation
Multiple
banks
544
3
3
—
691
83
27
5
8
1
Decimation
Multiple
banks;
Write
636
3
3
—
677
82
27
5
8
1
Fractional
Rate
—
1,165 5
4
—
1,715
205
27
5
8
1
Fractional
Rate
Write
1,287 5
4
—
1,770
198
27
5
8
1
Interpolation —
381
5
0
—
433
42
24
8
8
1
Interpolation Write
513
5
0
—
540
26
25
0
8
1
Single Rate
—
493
10
0
—
191
18
24
9
8
1
Single Rate
Write
624
10
0
—
563
26
25
1
UG-01072
2014.12.15
FIR II IP Core Performance and Resource Utilization
1-7
About the FIR II IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
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- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
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- Floating-Point (157 pages)
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- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
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- Parallel Flash Loader IP (57 pages)
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- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
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- DCFIFO (28 pages)