Altera FIR Compiler II MegaCore Function User Manual
Page 7
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Parameters
ALM
DSP
Blocks
Memory
Registers
f
MAX
(MHz)
Channel
Wires
Filter Type
Coefficients
M10K M20K Primary Secondary
8
2
Decimation
Write
2,120 24
0
—
1,298
141
30
8
8
2
Fractional
Rate
—
1,395 16
0
—
2,074
99
28
1
8
2
Fractional
Rate
Write
1,745 16
0
—
2,171
91
28
2
8
2
Fractional
Rate
—
1,493 16
0
—
2,167
117
28
0
8
2
Fractional
Rate
Write
1,852 16
0
—
2,287
116
27
0
8
2
Interpolation —
1,841 32
0
—
2,429
52
28
2
8
2
Interpolation Write
1,994 32
0
—
2,826
41
27
8
8
2
Interpolation Multiple
banks
2,001 32
0
—
2,737
74
27
9
8
2
Interpolation Multiple
banks;
Write
2,700 32
0
—
2,972
130
28
2
8
2
Single rate
—
932
20
0
—
318
20
27
8
8
2
Single rate
Write
1,057 20
0
—
713
3
27
9
8
1
Decimation
—
329
3
1
—
321
33
30
1
8
1
Decimation
Write
430
3
1
—
366
34
30
7
8
1
Decimation
Multiple
banks
395
3
3
—
483
44
31
0
8
1
Decimation
Multiple
banks;
Write
510
3
3
—
472
40
29
1
8
1
Fractional
Rate
—
661
5
4
—
877
75
31
0
8
1
Fractional
Rate
Write
788
5
4
—
936
98
30
9
1-4
FIR II IP Core Performance and Resource Utilization
UG-01072
2014.12.15
Altera Corporation
About the FIR II IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)