Altera FIR Compiler II MegaCore Function - Manual (Page 2)

Contents
About the FIR II IP Core.....................................................................................1-1
Altera DSP IP Core Features...................................................................................................................... 1-1
FIR II IP Core Features............................................................................................................................... 1-2
DSP IP Core Device Family Support.........................................................................................................1-2
DSP IP Core Verification............................................................................................................................1-3
FIR II IP Core Release Information...........................................................................................................1-3
FIR II IP Core Performance and Resource Utilization...........................................................................1-3
FIR II IP Core Getting Started............................................................................2-1
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
FIR II IP Core OpenCore Plus Timeout Behavior...................................................................... 2-2
IP Catalog and Parameter Editor...............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-3
Files Generated for Altera IP Cores...............................................................................................2-5
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-8
DSP Builder Design Flow............................................................................................................................2-9
FIR II IP Core Parameters.................................................................................. 3-1
Filter Specification Parameters.................................................................................................................. 3-1
Coefficient Parameters................................................................................................................................ 3-3
Loading Coefficients from a File................................................................................................................3-3
Input and Output Options..........................................................................................................................3-4
Signed Fractional Binary.................................................................................................................3-5
MSB and LSB Truncation, Saturation, and Rounding............................................................................3-6
Memory and Multiplier Trade-Offs..........................................................................................................3-6
Using CDelay RAM Block Threshold........................................................................................... 3-7
Using CDual Mem Dist RAM Threshold.....................................................................................3-7
Using M-RAM Threshold...............................................................................................................3-8
Using Hard Multiplier Threshold..................................................................................................3-8
FIR II IP Core Functional Description...............................................................4-1
FIR II IP Core Interfaces and Signals........................................................................................................4-1
Avalon-ST Interfaces in DSP IP Cores..........................................................................................4-2
FIR II IP Core Avalon-ST Interfaces.............................................................................................4-2
FIR II IP Core Signals......................................................................................................................4-8
FIR II IP Core Time-Division Multiplexing.......................................................................................... 4-11
FIR II IP Core Multichannel Operation................................................................................................. 4-12
Vectorized Inputs...........................................................................................................................4-12
Channelization............................................................................................................................... 4-13
TOC-2 FIR II IP Core User Guide
Altera Corporation