Altera FIR Compiler II MegaCore Function User Manual
Page 51
Figure 4-23: Correct Input Format (11 valid cycles, 9 invalid cycles)
areset
clk
xin_v[0]
xin_c[7:0]
xin_0[7:0]
xin_1[7:0]
xout_v[0]
xout_c[7:0]
xout_0[17:0]
xout_1[17:0]
xout_2[17:0]
xout_3[17:0]
xout_4[17:0]
xout_5[17:0]
xout_6[17:0]
xout_7[17:0]
xout_8[17:0]
xout_9[17:0]
xout_10[17:0]
1
0
1
1
2
3
4
5
6
7
8
9
10
11
4
1
2
3
4
5
6
7
12
13
14
15
16
17
18
19
20
21
22
15
12
13
14
15
16
17
18
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8
16
6
12
0
24
32
18
24
0
40
48
30
36
0
56
64
42
48
0
72
80
54
60
0
88
96
66
72
0
104
112
78
84
0
120
128
90
96
0
136
144
102
108
0
152
160
114
120
0
168
176
126
132
0
Figure 4-24: Incorrect Input Format (11 valid cycles, 0 invalid cycles)If the number of invalid cycles is
less than 17, the output format is incorrect.
areset
clk
xin_v[0]
xin_c[7:0]
xin_0[7:0]
xin_1[7:0]
xout_v[0]
xout_c[7:0]
xout_0[17:0]
xout_1[17:0]
xout_2[17:0]
xout_3[17:0]
xout_4[17:0]
xout_5[17:0]
xout_6[17:0]
xout_7[17:0]
xout_8[17:0]
xout_9[17:0]
xout_10[17:0]
1 2
3 4 5
6 7
8 9 10 11 1 2
3 4 5
6 7 8
9 10 11
0
150 186 177 92 178 50 112 220 132 3 111 100 215 142
12 13 14 15 16 17 18 19 20 21 22 12 13 14 15 16 17 18 19 20 21 22
0
206 172 212 214 18 255 190 91 36 129 163 193 149 0
0
1
00 01 00 01 00 01 00 01 00 01
0
1 0 1
6
12 0
18
24 0
30
36 0
42
48 0
54
60 0
66
72 0
78
84 0
90
96 0
102
108 0
114
120 0
126
132 0
4-18
22 Channels with 11 Valid Cycles and 9 Invalid Cycles
UG-01072
2014.12.15
Altera Corporation
FIR II IP Core Functional Description