Cirrus Logic CS8427 - Manual (Page 57)

CS8427
DS477F5 57
20.3 Component Value Selection
When transitioning from one revision of the part
another, component values may need to be
changed. While it is mandatory for customers to
change the external PLL component values when
transitioning from revision A to revision A1 or from
revision A to revision A2, customers do not need to
change external PLL component values when tran-
sitioning from revision A1 to revision A2, unless the
part is used in an application that is required to
pass the AES3 or IEC60958-4 specification for re-
ceiver jitter tolerance (see Table 7).
20.3.1 Identifying the Part Revision
The first line of the part marking on the package in-
dicates the part number and package type
(CS8427-xx). Table 5 shows a list of part revisions
and their corresponding second line part marking,
which indicates what revision the part is.
20.3.2 Locking to the RXP/RXN Receiver
Inputs
CS8427 parts that are configured to lock to only
the RXP/RXN receiver inputs should use the exter-
nal PLL component values listed in Table 6 and
Table 7. Values listed for the 32 to 96 kHz Fs
range will have the highest corner frequency jitter
attenuation curve, take the shortest time to lock,
and offer the best output jitter performance.
Revision
Pre-October 2002
SOIC & TSSOP (10-Digit)
New SOIC
(12-Digit)
New TSSOP
(10-Digit)
A Zxxxxxxxxx ZFBAAXxxxxxx NAAXxxxxxx
A1 Rxxxxxxxxx RFBAA1xxxxxx NAA1xxxxxx
A2 N/A RFBAA2xxxxxx NAA2xxxxxx
Table 5. Second Line Part Marking
Revision R
FILT
(k Ω) C
FILT
( μF) C
RIP
(nF) PLL Lock Time (ms)
A 0.909 1.8 33 56
A1 0.4 0.47 47 60
A2 0.4 0.47 47 60
Table 6. Locking to RXP/RXN - Fs = 8 to 96 kHz
Revision R
FILT
(k Ω) C
FILT
( μF) C
RIP
(nF) PLL Lock Time (ms)
A* 3.0 0.047 2.2 35
A1* 1.2 0.1 4.7 35
A2 1.2 0.1 4.7 35
A2* 1.6 0.33 4.7 35
Table 7. Locking to RXP/RXN - Fs = 32 to 96 kHz
* Parts used in applications that are required to pass the AES3 or IEC60958-4 specification for re-
ceiver jitter tolerance should use these component values. Please note that the AES3 and IEC60958
specifications do not have allowances for locking to sample rates less than 32 kHz or for locking to
the ILRCK input. Also note that many factors can affect jitter performance in a system. Please follow
the circuit and layout recommendations outlined previously.