Cirrus Logic CS8427 - Manual

1
Copyright  Cirrus Logic, Inc. 2010
(All Rights Reserved)
www.cirrus.com
CS8427
96 kHz Digital Audio Interface Transceiver
Features
 Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-compatible Transceiver
 +5.0 V Analog Supply (VA+)
 +3.3 V or +5.0 V Digital Interface (VL+)
 Flexible 3-wire Serial Digital I/O Ports
 Adjustable Sample Rate up to 96 kHz
 Low-jitter Clock Recovery
 Pin and Microcontroller Read/Write Access to
Channel Status and User Data
 Microcontroller and Standalone Modes
 Differential Cable Driver and Receiver
 On-chip Channel Status and User Data Buffer
Memories Permit Block Reads & Writes
 OMCK System Clock Mode
 Decodes Audio CD Q Sub-code
General Description
The CS8427 is a stereo digital audio transceiver with
AES3 and serial digital audio inputs, AES3 and serial
digital audio outputs, and includes comprehensive con-
trol ability through a 4-wire microcontroller port. Channel
status and user data are assembled in block-sized buff-
ers, making read/modify/write cycles easy.
A low-jitter clock recovery mechanism yields a very clean
recovered clock from the incoming AES3 stream.
Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and au-
tomotive audio systems.
The CS8427 is available in 28-pin SOIC and TSSOP
packages in Commercial (-10°C to +70°C) and Automo-
tive (-40°C to +85°C) grades. The CDB8427 Customer
Demonstration Board is also available for device evalu-
ation and implementation suggestions. Please see
“Ordering Information” on page 49 for complete details.
I
Serial
Audio
Input
Clock &
Data
Recovery
Misc.
Control
AES3
S/PDIF
Encoder
Serial
Audio
Output
Receiver
AES3
S/PDIF
Decoder
C & U bit
Data
Buffer
Control
Port &
Registers
Output
Clock
Generator
RXN
RXP
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUT
TXP
TXN
RST OMCK EMPH U TCBL SDA/
CDOUT
SCL/
CCLK
AD1/
CDIN
AD0/
CS
INT
VA+ AGND FILT RERR VL+ DGND
H/S
RMCK
Driver
MAY ‘10
DS477F5