Cirrus Logic CS8427 - Manual (Page 45)

CS8427
DS477F5 45
ILRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on
the SDIN pin.
ISCLK 13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
SDIN 14 Serial Audio Data Port (Input) - Audio data serial input pin.
TCBL 15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is
high during the first sub-frame of a transmitted channel status block, and low at all other times.
When operated as input, driving TCBL high for at least three OMCK clocks will cause the next
transmitted sub-frame to be the start of a channel status block.
OSCLK 16 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT
pin
OLRCK 17 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on
the SDOUT pin. Frequency will be the output sample rate (Fs)
SDOUT 18 Serial Audio Output Data (Output) - Audio data serial output pin
AUDIO/V 19 Audio Channel Status Bit / V-Bit (Input/Output) - Reflects either the state of the audio/non-
audio Channel Status bit in the incoming AES3 data stream or is the Validity bit data input for
the AES3 transmitted data stream, clocked by OLRCK.
PRO/C 20 PRO Channel Status Bit / C-Bit (Input/Output) - Reflects either the state of the Profes-
sional/Consumer Channel Status bit in the incoming AES3 data stream or is the serial C-bit
input for the AES3 transmitted data, clocked by OLRCK.
APMS 21 Serial Audio Input Port Master/Slave Select (Input) - APMS should be connected to VL+ to
set serial audio input port as a master, or connected to DGND to set the port as a slave.
VL+
VL2+ 23
27 Positive Digital Power (Input) - Typically +3.3 V or +5.0 V.
H/S 24 Hardware/Software Mode Control (Input) - Determines the method of controlling the opera-
tion of the CS8427, and the method of accessing CS and U data. In software mode, device
control and CS and U data access is primarily through the control port, using a microcontroller.
Hardware mode provides an alternate mode of operation and access to the CS and U data
through dedicated pins.
This pin should be permanently tied to VL+ or DGND
TXP
TXN 25
26 Differential Line Driver (Output) - Drivers transmit AES3 data and are pulled low while the
CS8427 is in the reset state.
ORIG 28 ORIG Channel Status Bit (Output) - SCMS generation indicator. This is decoded from the
incoming category code and the L bit. A low output indicates that the source of the audio data
stream is a copy. A high indicates that the source of the audio data stream is an original
recording. This is also a start-up option pin, and requires a pull-up or pull-down resistor.