Cirrus Logic CS8427 - Manual (Page 31)

CS8427
DS477F5 31
11.5 Serial Audio Input Port Data Format (05h)
SIMS - Master/Slave Mode Selector
Default = ‘0’
0 - Serial audio input port is in slave mode
1 - Serial audio input port is in master mode
SISF - ISCLK frequency (for master mode)
Default = ‘0’
0 - 64 * Fsi
1 - 128 * Fsi
SIRES1:0 - Resolution of the input data, for right-justified formats
Default = ‘00’
00 - 24 bit resolution
01 - 20 bit resolution
10 - 16 bit resolution
11 - Reserved
SIJUST - Justification of SDIN data relative to ILRCK
Default = ‘0’
0 - Left-justified
1 - Right-justified
SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats
Default = ‘0’
0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge
1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge
SISPOL - ISCLK clock polarity
Default = ‘0’
0 - SDIN sampled on rising edges of ISCLK
1 - SDIN sampled on falling edges of ISCLK
SILRPOL - ILRCK clock polarity
Default = ‘0’
0 - SDIN data is for the left channel when ILRCK is high
1 - SDIN data is for the right channel when ILRCK is high
11.6 Serial Audio Output Port Data Format (06h)
SOMS - Master/Slave Mode Selector
Default = ‘0’
0 - Serial audio output port is in slave mode
1 - Serial audio output port is in master mode
SOSF - OSCLK frequency (for master mode)
Default = ‘0’
0 - 64 * Fso
1 - 128 * Fso
7 6 5 4 3 2 1 0
SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL
7 6 5 4 3 2 1 0
SOMS SOSF SORES1 SORES0 SOJUST SODEL SOSPOL SOLRPOL