Cirrus Logic CS8416 User Manual

192 khz digital audio interface receiver, Cs8416, Features

Table of contents

Document Outline

1. Characteristics and Specifications
- Specified Operating Conditions
- Absolute Maximum Ratings
- DC Electrical Characteristics
- Digital Input Characteristics
- Digital Interface Specifications
- Switching Characteristics
- Switching Characteristics - Serial Audio Ports
  - Figure 1. Audio Port Master Mode Timing
  - Figure 2. Audio Port Slave Mode and Data Input Timing
- Switching Characteristics - Control Port - SPI Mode
  - Figure 3. SPI Mode Timing
- Switching Characteristics - Control Port- I·C Format
  - Figure 4. I·C Mode Timing
2. Pin Description - Software Mode
- 2.1 TSSOP Pin Description
- 2.2 QFN Pin Description
3. Pin Description - Hardware Mode
- 3.1 TSSOP Pin Description
- 3.2 QFN Pin Description
4. Typical Connection Diagrams
- Figure 5. Typical Connection Diagram - Software Mode
- Figure 6. Typical Connection Diagram - Hardware Mode
5. Applications
- 5.1 Reset, Power-Down and Start-Up
- 5.2 ID Code and Revision Code
- 5.3 Power Supply, Grounding, and PCB Layout
6. General Description
- 6.1 AES3 and S/PDIF Standards Documents
7. Serial Audio Output Port
- Figure 7. Serial Audio Output Example Formats
- 7.1 Slip/Repeat Behavior
  - Figure 8. AES3 Data Format
- 7.2 AES11 Behavior
  - Table 1. Typical Delays by Frequency Values
8. S/PDIF Receiver
- Figure 9. Receiver Input Structure
- 8.1 8:2 S/PDIF Input Multiplexer
- 8.2 OMCK System Clock Mode
  - Table 2. Clock Switching Output Clock Rates
- 8.3 Clock Recovery and PLL Filter
9. General Purpose Outputs
- Table 3. GPO Pin Configurations
10. Error and Status Reporting
- 10.1 General
  - 10.1.1 Software Mode
  - 10.1.2 Hardware Mode
- 10.2 Non-Audio Detection
  - 10.2.1 Format Detection
- 10.3 Interrupts
11. Channel Status and User-Data Handling
- 11.1 Software Mode
- 11.2 Hardware Mode
  - Figure 10. C/U Data Outputs
12. Control Port Description
- 12.1 SPI Mode
  - Figure 11. Control Port Timing in SPI Mode
- 12.2 I·C Mode
  - Figure 12. Control Port Timing, I·C Slave Mode Write
  - Figure 13. Control Port Timing, I·C Slave Mode Read
13. Control Port Register Quick Reference
14. Control Port Register Descriptions
- 14.1 Memory Address Pointer (MAP)
- 14.2 Control0 (00h)
- 14.3 Control1 (01h)
- 14.4 Control2 (02h)
  - Figure 14. De-Emphasis Filter Response
- 14.5 Control3 (03h)
- 14.6 Control4 (04h)
- 14.7 Serial Audio Data Format (05h)
- 14.8 Receiver Error Mask (06h)
- 14.9 Interrupt Mask (07h)
- 14.10 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h)
- 14.11 Receiver Channel Status (0Ah)
- 14.12 Format Detect Status (0Bh)
- 14.13 Receiver Error (0Ch)
- 14.14 Interrupt 1 Status (0Dh)
- 14.15 Q-Channel Subcode (0Eh - 17h)
- 14.16 OMCK/RMCK Ratio (18h)
- 14.17 Channel Status Registers (19h - 22h)
- 14.18 IEC61937 PC/PD Burst Preamble (23h - 26h)
- 14.19 CS8416 I.D. and Version Register (7Fh)
15. Hardware Mode
- 15.1 Serial Audio Port Formats
  - Figure 15. Hardware Mode Data Flow
- 15.2 Hardware Mode Function Selection
  - Table 4. Hardware Mode Start-Up Pin Conditions
- 15.3 Hardware Mode Equivalent Register Settings
  - Table 5. Hardware Mode Serial Audio Format Select
16. External AES3/SPDIF/IEC60958 Receiver Components
- 16.1 AES3 Receiver External Components
- 16.2 Isolating Transformer Requirements
17. Channel Status Buffer Management
- 17.1 AES3 Channel Status (C) Bit Management
- 17.2 Accessing the E Buffer
  - 17.2.1 Serial Copy Management System (SCMS)
    - Figure 21. Channel Status Data Buffer Structure
    - Figure 22. Flowchart for Reading the E Buffer
18. PLL Filter
- 18.1 General
  - Figure 23. PLL Block Diagram
- 18.2 External Filter Components
19. Package Dimensions
- TSSOP Thermal Characteristics
- QFN Thermal Characteristics
20. Ordering Information
21. Revision History