Cirrus Logic CS8416 - Manual (Page 9)

DS578F3 9
CS8416
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
Notes:
8. In Software Mode the active edges of OSCLK are programmable.
9. In Software Mode the polarity of OLRCK is programmable.
10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
Parameter Symbol Min Typ Max Units
OSCLK/OLRCK Active Edge to SDOUT Output Valid (Note 8) t
dpd
- - 23 ns
Master Mode
RMCK to OSCLK active edge delay
(Note 8) t
smd
0 - 12 ns
RMCK to OLRCK delay (Note 9) t
lmd
0 - 12 ns
OSCLK and OLRCK Duty Cycle - 50 - %
Slave Mode
OSCLK Period
t
sckw
36 - - ns
OSCLK Input Low Width t
sckl
14 - - ns
OSCLK Input High Width t
sckh
14 - - ns
OSCLK Active Edge to OLRCK Edge (Notes 8,9,10) t
lrckd
10 - - ns
OSCLK Edge Setup Before OSCLK Active-Edge (Notes 8,9,11) t
lrcks
10 - - ns
Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input
sckh sckl
sckw t
t t
tdpd
SDOUT
(input)
(input)
lrcks
t lrckd
t
OSCLK
OLRCK
t smd
t lmd
O S C LK
(output)
O LR C K
(output)
R M C K
(output)