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Spw-10x spacewire router, User manual, Preliminary – Atmel SpaceWire Router SpW-10X User Manual

Page 11

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Ref.: UoD_SpW-10X_

UserManual

Issue: 3.4

SpW-10X

SpaceWire Router

User Manual

Date: 11

th

July 2008

Preliminary

11

F

IGURE

8-8

A

RBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY

(1) .......................................................... 89

F

IGURE

8-9

A

RBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY

(2) .......................................................... 91

F

IGURE

8-10

N

ORMAL GROUP ADAPTIVE ROUTING

................................................................................................ 92

F

IGURE

8-11

G

ROUP ADAPTIVE ROUTING WHEN OTHER PORTS BUSY

..................................................................... 93

F

IGURE

8-12

G

ROUP ADAPTIVE ROUTING WHEN PORTS NOT READY

...................................................................... 93

F

IGURE

8-13

P

ACKET

S

ELF

-A

DDRESSING MODE

.................................................................................................... 94

F

IGURE

8-14

D

ESTINATION

N

ODE

B

LOCKED

(

A

).................................................................................................... 96

F

IGURE

8-15

D

ESTINATION

N

ODE

B

LOCKED

(

B

).................................................................................................... 96

F

IGURE

8-16

D

ESTINATION

N

ODE

B

LOCKED

(

C

).................................................................................................... 97

F

IGURE

8-17

D

ESTINATION

N

ODE

B

LOCKED

:

W

ATCHDOG

M

ODE

(

A

).................................................................... 97

F

IGURE

8-18

D

ESTINATION

N

ODE

B

LOCKED

:

W

ATCHDOG

M

ODE

(

B

).................................................................... 97

F

IGURE

8-19

D

ESTINATION

N

ODE

B

LOCKED

:

W

ATCHDOG

M

ODE

(

C

).................................................................... 98

F

IGURE

8-20

D

ESTINATION

N

ODE

B

LOCKED

:

W

ATCHDOG

M

ODE

(

D

).................................................................... 98

F

IGURE

8-21

S

OURCE

N

ODE

S

TALLED

(

A

) ............................................................................................................. 99

F

IGURE

8-22

S

OURCE

N

ODE

S

TALLED

(

B

).............................................................................................................. 99

F

IGURE

8-23

S

OURCE

N

ODE

S

TALLED

(

C

).............................................................................................................. 99

F

IGURE

8-24

S

OURCE

N

ODE

S

TALLED

(

D

) ............................................................................................................. 99

F

IGURE

8-25

S

OURCE

N

ODE

S

TALLED

:

W

ATCHDOG

M

ODE

(

A

) ........................................................................... 100

F

IGURE

8-26

S

OURCE

N

ODE

S

TALLED

:

W

ATCHDOG

M

ODE

(

B

)............................................................................ 100

F

IGURE

8-27

S

OURCE

N

ODE

S

TALLED

:

W

ATCHDOG

M

ODE

(

C

)............................................................................ 100

F

IGURE

8-28

S

OURCE

N

ODE

S

TALLED

:

W

ATCHDOG

M

ODE

(

D

) ........................................................................... 100

F

IGURE

9-1

R

OUTER

I

NTERNAL

M

EMORY

M

AP

................................................................................................... 103

F

IGURE

9-2

GAR

R

EGISTER

F

IELDS

..................................................................................................................... 105

F

IGURE

9-3

S

PACE

W

IRE

P

ORT

C

ONTROL

/S

TATUS

R

EGISTER

F

IELDS

................................................................... 112

F

IGURE

9-4

N

ETWORK

D

ISCOVERY

R

EGISTER

F

IELDS

......................................................................................... 116

F

IGURE

9-5

R

OUTER

C

ONTROL

R

EGISTER

F

IELDS

................................................................................................ 117

F

IGURE

9-6

E

RROR

A

CTIVE

R

EGISTER

F

IELDS

..................................................................................................... 120

F

IGURE

9-7

T

IME

-C

ODE

R

EGISTER

F

IELDS

.......................................................................................................... 121

F

IGURE

9-8

D

EVICE

M

ANUFACTURER AND

C

HIP

ID

R

EGISTER

F

IELDS

................................................................ 122

F

IGURE

9-9

T

IME

-C

ODE

E

NABLE

R

EGISTER

F

IELDS

............................................................................................. 123

F

IGURE

9-10

T

RANSMIT CLOCK CONTROL REGISTER

........................................................................................... 125

F

IGURE

10-1

DS

MINIMUM CONSECUTIVE EDGE SEPARATION

.............................................................................. 128

F

IGURE

10-2

E

XTERNAL PORT INPUT

FIFO

TIMING PARAMETERS

........................................................................ 129

F

IGURE

10-3

E

XTERNAL PORT OUTPUT

FIFO

TIMING PARAMETERS

..................................................................... 129

F

IGURE

10-4

T

IME

-C

ODE

I

NPUT

I

NTERFACE

........................................................................................................ 130

F

IGURE

10-5

T

IME

-C

ODE

O

UTPUT

I

NTERFACE

.................................................................................................... 131

F

IGURE

10-6

T

IME

-

CODE

TIME_CTR_RST

INTERFACE

...................................................................................... 131

F

IGURE

12-1

PLL

L

AYOUT

R

ECOMMENDATIONS

................................................................................................. 142

F

IGURE

13-1

R

ESET

W

AVEFORM

......................................................................................................................... 146

F

IGURE

13-2

R

ESET

W

AVEFORM WITH

D

ATA AND

S

TROBE

B

OTH

H

IGH

.............................................................. 146

F

IGURE

13-3

G

LITCHES ON

D

ATA OR

S

TROBE DURING

R

ESET

............................................................................. 146

F

IGURE

13-4

S

IMULTANEOUS

T

RANSITION OF

D

ATA AND

S

TROBE DURING

R

ESET

.............................................. 146