GW Instek PSW-Series Programming & Command manual - Manual (Page 101)

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101
Standard Event Status Register Group
Overview The Standard Event Status Register Group
indicates if any errors have occurred. The bits
of the Event register are set by the error event
queue.
OPC
RQC
QUE
DDE
EXE
CME
URQ
PON
Event Enable
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Standard Event Status Register
&
&
&
&
&
&
&
&
To Status Byte Register
*ESR?
Logical OR
*ESE
*ESE?
Bit Summary
Event Bit #
Bit
Weight
OPC (Operation complete)
The OCP bit is set when all
selected pending operations are
complete. This bit is set in
response to the *OPC command.
0 1
RQC (Request control) 1 2
QUE (Query Error)
The Query Error bit is set in
response to an error reading the
Output Queue. This can be
caused by trying to read the
Output Queue when there is no
data present.
2 4
DDE (Device Dependent Error)
Device specific error.
3 8