Atec Agilent-16700 Series - Manual (Page 90)

90
State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,
16750B, 16751B, 16752B Supplemental Specifications* and Characteristics
State Mode 16715A, 16716A, 16717A 16740A, 16741A, 16742A
167 Mb/s State Mode 16750B, 16751B, 16752B
200 Mb/s State Mode
Maximum state acquisition rate on 167 Mb/s 200 Mb/s
each channel
Channel count 68 per module 68 per module
Maximum channels on a single 340 340
time base and trigger
Number of independent analyzers 2, can be set up in state or timing modes 2, can be set up in state or timing modes
Minimum master to 5.988 ns 5 ns
master clock time* [1]
Minimum master to slave clock time 2 ns 2 ns
Minimum slave to master clock time 2 ns 2 ns
Minimum slave to slave clock time 5.988 ns 5 ns
Setup/hold time* [1] 2.5 ns window adjustable from 4.5/-2.0 ns to 2.5 ns window adjustable from 4.5/-2.0 ns to
(single-clock, single-edge) -2.0/4.5 ns in 100 ps increments per channel -2.0/4.5 ns in 100 ps increments per channel
Setup/hold time* [1] 3.0 ns window adjustable from 5.0/-2.0 ns to 3.0 ns window adjustable from 5.0/-2.0 ns to
(multi-clock, multi-edge) -1.5/4.5 ns in 100 ps increments per channel -1.5/4.5 ns in 100 ps increments per channel
Setup/hold time (on individual channels, 1.25 ns window 1.25 ns window
after running eye finder)
Minimum state clock pulse width 1.2 ns 1.2 ns
Time tag resolution [2] 4 ns 4 ns
Maximum time count between states 17 seconds 17 seconds
Maximum state tag count 232 232
between states [2]
Number of state clocks/qualifiers 4 4
Maximum memory depth 16716A: 512K 16740A: 1M 16750B: 4M
16715A, 16717A: 2M 16741A: 4M 16751B: 16M
16742A: 16M 16752B: 32M
Maximum trigger sequence speed 167 MHz 200 MHz
Maximum trigger sequence levels 16 16
* All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] Tested at input signal VH=-0.9V, VL=-1.7V, Slew rate=1V/ns, and threshold=-1.3V.
[2] Time or state tags halve the acquisition memory when there are no unassigned pods.