Atec Agilent-16700 Series - Manual (Page 86)

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Key Specifications* and Characteristics (continued)
Agilent Model Number 16710A, 16711A, 16712A 16753A, 16754A, 16755A, 16756A
Maximum state acquisition rate on 100 Mb/s 600 Mb/s
each channel
Maximum timing sample rate Conventional: 500/250 MHz Timing Zoom: 4 GHz
(half/full channel) Transitional: 125 MHz Conventional: 1200/600 MHz
Transitional: 600 MHz
Channels/module 102 68
Maximum channel count on a 204 (2 modules) 340 (5 modules)
single time base and trigger
Memory depth 16710A: 16/8K [1] 16753A: 2/1M [1]
(half/full channel) 16711A: 64/32K [1] 16754A: 8/4M [1]
16712A: 256/128k [1] 16755A: 32/16M [1]
16756A: 128/64M [1]
Trigger resources Patterns: 10 Patterns: 16
Ranges: 2 Ranges: 15
Edge & Glitch: 2 Edge & Glitch: 2
Timers: 2 Timers: (2 per module) -1
Occurrence Counter: [3]
Global Counters: 2
Flags: 4
Maximum trigger sequence levels State mode: 12 Patterns: 16
Timing mode: 10 Ranges: 15
Edge & Glitch: 2
Timers: (2 per module) -1
Occurrence Counter: [3]
Global Counters: 2
Flags: 4
Maximum trigger sequence speed 125 MHz 600 MHz
Trigger sequence level branching Dedicated next state or 4-way arbitrary
single arbitrary branching “IF/THEN/ELSE” branching
Number of state clocks/qualifiers 6 4
Setup/hold time* 4.0 ns window adjustable from 1 ns window (600ps typical) adjustable
4.0/0 ns to 0/4.0 ns in 500 ps in 80ps increments
increments [2] per 34 channels
Threshold range TTL, ECL, user-definable ±6.0 V -3.0 V to +5.0 V adjustable in
adjustable in 50 mV increments 10-mV increments
* All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] Memory depth doubles in half-channel timing mode only.
[2] Minimum setup/hold time specified for single-clock, single-edge acquisition. Single-clock, multi-edge setup/hold add 0.5 ns.
Multi-clock, multi-edge setup/hold window add 1.0 ns.
[3] There is one occurrence counter per trigger sequence level.
State/Timing Modules Specifications and
Characteristics