Rainbow Electronics DS2182A - Manual (Page 12)

DS2182A
041995 12/22
SYNC CRITERIA (RCR1.3)
193E. Bit RCR1.3 determines which sync algorithm is
utilized when resync is in progress (RLOS = 1). In 193E
framing, when RCR1.3 = 0, the synchronizer will lock
only to the FPS pattern and will move to the new frame
and multiframe alignment after the framing candidate is
qualified. RLOS will go low one frame after the move to
the new alignment. When RCR1.3 = 1, the new align-
ment is further tested by a CRC6 code match. RLOS will
transition low after a CRC6 match occurs. If no CRC6
match occurs in three attempts (three multiframes), the
algorithm resets and a new search for the FPS pattern
begins. It takes 9 ms for the synchronizer to check the
first CRC6 code after the new FPS alignment has been
loaded. Each additional CRC6 test takes 3 ms. Regard-
less of the state of RCR1.3, if more than one candidate
exists after 24 ms, the synchronizer begins eliminating
emulators by testing their CRC6 codes in order to find
the true framing candidate.
193S. In 193S framing, when RCR1.3 = 1, the synchro-
nizer cross-checks the FT pattern with the FS pattern to
help eliminate false framing candidates such as digital
milliwatts. The FS patterns are compared to the repeat-
ing pattern ...00111000111000...(00111x0 if RCR2.3 =
1). In this mode, FT and FS must be correctly identified
by the synchronizer before sync is declared. Clearing
RCR1.3 causes the synchronizer to search for the FT
pattern (101010...) without cross-coupling the FS pat-
tern. Frame sync is established using the FT informa-
tion, while multiframe sync is established only if valid FS
information is present. If no valid FS pattern is identified,
the synchronizer moves to the FT alignment, RLOS
goes low, and a false multiframe position may be indi-
cated by RMSYNC. RFER indicates when the received
S-bit pattern does not match the assumed internal multi-
frame alignment. This mode will be used in applications
where non-standard S-bit patterns exist. In such appli-
cations, multiframe alignment information can be de-
coded externally by using the S-bits present at RLINK.
SYNC TIME (RCR1.2)
Bit RCR1.2 determines the number of consecutive
framing pattern bits to be qualified before SYNC is de-
clared. If RCR1.2 =1, the algorithm validates 24 bits; if
RCR1.2 = 0, 10 bits are validated. Validating 24 bits re-
sults in superior false framing protection while 10-bit
testing minimizes reframe time. In either case, the syn-
chronizer only establishes resync when one and only
one candidate is found (see Table 5).
AVERAGE REFRAME TIME Table 5
FRAME
RCR1.2 = 0 RCR1.2 = 1
FRAME
MODE
MIN. AVG. MAX. MIN. AVG. MAX.
193S 3.0ms 3.75ms 4.5ms 6.5ms 7.25ms 8.0ms
193E 6.0ms 7.5ms 9.0ms 13.0ms 14.5ms 16.0ms
NOTE:
1. Average reframe time is defined here as the average time it takes from the start of resync (rising edge of
RLOS) to the actual loading of the new alignment (on a multiframe edge) into the output receive timing.
SYNC ENABLE (RCR1.1)
When RCR1.1 is cleared, the receiver initiates automat-
ic resync if an OOF event occurs or if carrier loss (192
consecutive 0s) occurs (depends on RCR1.7). When
RCR1.1 is set, the automatic resync circuitry is dis-
abled. In this case, resync can only be initiated by set-
ting RCR1.0 to 1 or externally transitioning RST from
low to high. Note that using RST to initiate a resync re-
sets the output timing while RST is low; use of RCR1.1
will not affect the output timing until the new alignment is
located.
RESYNC (RCR1.0)
A 0-to-1 transition of RCR1.0 causes the synchronizer
to search for the framing pattern sequence immediately,
regardless of the internal sync status. In order to initiate
another resync command, this bit must be cleared and
then set again.