Rainbow Electronics DS2182A - Manual (Page 11)

DS2182A
041995 11/22
CRCCS RIMR2.1 CRC Count Saturation Mask.
1 = interrupt enabled
0 = interrupt masked
BPVCS RIMR2.0 Bipolar Violation Count Saturation Mask.
1 = interrupt enabled
0 = interrupt masked
RCR1: RECEIVE CONTROL REGISTER 1 Figure 12
(MSB) (LSB)
ARC OOF1 OOF2 ACR SYNCC SYNCT SYNCE RESYNC
SYMBOL POSITION NAME AND DESCRIPTION
ARC RCR1.7 Auto Resync Criteria.
1 = resync on OOF event only
0 = resync on OOF event or Receive Carrier Loss (RCL)
OOF1 RCR1.6 Out Of Frame 1. OOF event description. Valid when RCR1.5 is cleared
1 = 2 out of 5 frame bits (FT or FPS) in error
0 = 2 out of 4 frame bits (FT or FPS) in error
OOF2 RCR1.5 Out Of Frame 2. OOF event description.
1 = 2 out of 6 frame bits (FT or FPS) in error
0 = follow OOF event described in RCR1.6
ACR RCR1.4 Auto Counter Reset. When set, all four of the counters will be reset to 0
when read.
SYNCC RCR1.3 Sync Criteria. Determines the type of algorithm utilized by the receive syn-
chronizer; differs for each frame mode.
193S Framing (RCR2.4 = 0)
0 = synchronize to frame boundaries using FT pattern, then search for mul-
tiframe by using FS.
1 = cross couple FT and FS patterns in sync algorithm.
193E Framing (RCR2.4 = 1)
0 = normal sync (utilizes FPS only).
1 = validate new alignment with CRC before declaring sync.
SYNCT RCR1.2 Sync Time.
1 = validate 24 consecutive F-bits before declaring sync.
0 = validate 10 consecutive F-bits before declaring sync.
SYNCE RCR1.1 Sync Enable. If clear, the DS2182A automatically begins a resync if the
conditions described in RCR1.7 are met. If set, no auto resync occurs.
RESYNC RCR1.0 Resync. When toggled low to high, the DS2182A initiates a resync imme-
diately. The bit must be cleared and set again for subsequent resyncs.
SYNCHRONIZER
The heart of the monitor is the receive synchronizer.
This circuit serves two purposes: 1) monitors the incom-
ing data stream for loss of frame or multiframe align-
ment, and 2) searches for new frame alignment pattern
when sync loss is detected. When sync loss is de-
tected, the synchronizer begins an off-line search for the
new alignment; all output timing signals remain at the
old alignment with the exception of RSIGFR, which is
forced low during resync. When one and only one can-
didate is qualified, the output timing moves to the new
alignment at the beginning of the next multiframe. One
frame later, RLOS will transition low, indicating valid
sync and the resumption of the normal sync monitoring
mode. Several bits in the RCR1 allow tailoring of the re-
sync algorithm by the user. These bits are described be-
low.