Rainbow Electronics T89C51CC01 - Manual (Page 35)

35
T89C51CC01
Rev. D – 17-Dec-01
9.3 Overview of FM0
operations The CPU interfaces to the flash memory through the FCON register and AUXR1
register.
These registers are used to:
• Map the memory spaces in the adressable space
• Launch the programming of the memory spaces
• Get the status of the flash memory (busy/not busy)
9.3.1 Mapping of the memory
space By default, the user space is accessed by MOVC instruction for read only. The column
latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a
page while bits 14 to 7 are used to select the programming address of the page.
Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-
dance with Table 9. A MOVC instruction is then used for reading these spaces.
Table 9. .FM0 blocks select bits
9.3.2 Launching programming FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5xh followed by Axh. Table 10 summarizes the memory
spaces to program according to FMOD1:0 bits.
FMOD1 FMOD0 FM0 Adressable space
0 0 User (0000h-FFFFh)
0 1 Extra Row(FF80h-FFFFh)
1 0 Hardware Security Byte (0000h)
1 1 reserved