Rainbow Electronics T89C51CC01 - Manual (Page 130)

130
T89C51CC01
Rev. D – 17-Dec-01
Table 92. IPL1 Register
IPL1 (S:F8h)
Interrupt Priority Low Register 1
Reset Value: XXXX X000b
bit addressable
7 6 5 4 3 2 1 0
- - - - POVRL PADCL PCANL
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 POVRL
Timer overrun Interrupt Priority level less significant bit.
Refer to PI2CH for priority level.
1 PADCL
ADC Interrupt Priority level less significant bit.
Refer to PSPIH for priority level.
0 PCANL
CAN Interrupt Priority level less significant bit.
Refer to PKBH for priority level.