Rainbow Electronics T89C51CC01 User Manual
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T89C51CC01
Rev. D – 17-Dec-01
Figure 9. External Code Memory Interface Structure
Table 7. External Code Memory Interface Signals
9.1.2 External Bus Cycles
This section describes the bus cycles the T89C51CC01 executes to fetch code (see
Figure 10) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
mation on X2 mode see section “Clock “.
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized
form and do not provide precise timing information.
For bus cycling parameters refer to the section "AC-DC parameters".
FLASH
EPROM
T89C51CC01
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
Latch
OE
PSEN#
Signal
Name
Type
Description
Alternate
Function
A15:8
O
Address Lines
Upper address lines for the external bus.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
P0.7:0
ALE
O
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
-
PSEN#
O
Program Store Enable Output
This signal is active low during external code fetch or external code read
(MOVC instruction).
-