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American Magnetics 286 Multi-Sensor Liquid Level Instrument (CE-Marked) User Manual

Page 86

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72

Remote Interface Reference

Status System Commands

SYSTem:ERRor?

Queries the instrument’s error buffer. Up to 10 errors are stored in the
instrument’s error buffer. Errors are retrieved in first-in-first-out (FIFO)
order. The error buffer is cleared by the

*CLS

(clear status) command or

when the power is cycled. Errors are also cleared as they are read. See
page 82 for a complete description of the error buffer and messages.

5.4.2

Status System Commands

The status system register groups and commands are illustrated in Figure
5-1 on page 62.

*STB?

Returns the contents of the Status Byte register. The command is executed
in the order received as any other command. It does not clear an SRQ
condition or the “Summary Bit” (bit 6) of the Status Byte register.

*SRE <

enable_value

>

Enables bits in the Status Byte register to be reported in the “Summary
Bit” (bit 6) of the Status Byte register. To enable bits, you must write a
decimal

<

enable_value

>

which corresponds to the binary-weighted sum of

the bits you wish to enable. Refer to Table 5-1 on page 63 for more
information. For example, to enable only channel 2 unmasked alarm
status in the "Summary Bit" of the Status Byte register, send the
command:

*SRE 2;

*SRE?

The

*SRE?

query returns a decimal sum which corresponds to the binary-

weighted sum of the bits enabled by the last

*SRE

command.

*CLS

Clears the Standard Event register and the error buffer.

*ESR?

Returns the contents of the Standard Event register as a binary-weighted
sum.

*ESE <

enable_value

>

Enables bits in the Standard Event register to be reported in the
“Standard Event” bit (bit 5) of the Status Byte register. To enable bits, you
must write a decimal

<

enable_value

>

which corresponds to the binary-

weighted sum of the bits you wish to enable. Refer to Table 5-2 on page 65
for more information. For example, to enable all categories of error
messages to be reported in bit 5 of the Status Byte register, send: