R61509V
Target
Spec
Rev. 0.11 April 25, 2008, page 51 of 181
ENC[2:0]: Sets the RAM write cycle via RGB interface.
Table 21
ENC[2:0]
RAM Write Cycle (frame periods)
3’h0 1
frame
3’h1 2
frames
3’h2 3
frames
3’h3 4
frames
3’h4 5
frames
3’h5 6
frames
3’h6 7
frames
3’h7 8
frames
