Renesas R61509V - Manual (Page 129)

R61509V Target Spec
Rev. 0.11 April 25, 2008, page 129 of 181
RAM Address and Display Position on the Panel
The R61509V has memory to store display data of 240RGB x 432 lines. The R61509V incorporates a
circuit to control partial display, which allows switching driving method between full-screen display mode
and partial display mode.
The R61509V makes display arrangement setting and panel driving position control setting separately and
specifies RAM area for each image displayed on the panel.
The following is the sequence of setting full-screen and partial display.
1. Set (PTSA, PTEA) to specify the RAM area for each partial image
2. Set the display position of each partial image on the base image by setting PTDP.
3. Set NL to specify the number of lines to drive the liquid crystal panel to display the base
image
4. After display ON, set display enable bits (BASEE, PTDE) to display respective images
Normal display BASEE = 1, PTDE = 0
Partial display BASEE = 0, PTDE = 1
5.
Changes BASEE, PTDE settings when turning on and off the full and partial displays 1/2.
In driving the liquid crystal panel, the clock signal for gate line scan is supplied consecutively via interface
in accordance with the number of lines to drive the liquid crystal panel (NL setting).
When switching the display position in horizontal direction, set SS bit when writing RAM data.
Table 65
Display ENABLE Numbers of lines RAM area
Base image BASEE NL (VSA, VEA)
Note: The base image is displayed from the first line of the screen.
Table 66
Display ENABLE Display position RAM area
Partial image PTDE PTDP (PTSA, PTEA)