Renesas R61509V User Manual
Page 123
R61509V
Target
Spec
Rev. 0.11 April 25, 2008, page 123 of 181
Setting Example of Display Control Clock in RGB Interface Operation
Register
The display operation via DPI is performed in synchronization with the internal clock (PCLKD) that is
generated by dividing PCLK frequency.
PCDIVH[3:0]: When PCLKD is High, the number of clocks is set in unit of 1 clock.
PCDIVL[3:0]: When PCLKD is Low, the number of clocks is set in unit of 1 clock.
PCDIVH and PCDIVL (division ratio setting registers) should be set so that the difference between
PCLKD frequency and the internal oscillation clock (678kHz) is minimized.
Set PCDIVL to PCDIVH or PCDIVH
− 1.
Make sure (number of PCLK frequency)
≥ (number of RTN clocks) ∗ (division ratio of DIV) ∗ (PCDIVH +
PCDIVL)
Setting example (frame frequency: 60Hz)
Internal clock:
Internal oscillation clock
= 678kHz
1/1 Div.
= (DIVE[2:0] = 2’b0)
HFP
= 10 clocks
FP
= 8’h8, BP = 8’h8, NL = 6B (432 lines)
Æ 59.35Hz
PCLK: Hsync
= 10 clocks
HBP = 20 clocks
HFP = 10 clocks
60Hz
× (8+432+8) lines (10+20+240+10) clocks = 7.53MHz
PCLK frequency
= 7.53MHz
7.53MHz/678kHz
= 11.11 (Set PCDIVH and PCDIVL so that PCLK frequency is divided into
11.)
7.53/11
= 685kHz
685kHz / 25 clocks / 448 lines
= 61.2Hz
PCDIVH = 4’h6
PCDIVL = 4’h5
㪧㪚㪛㪠㪭㪟㪔㪋㩾㪿㪍
㪧㪚㪛㪠㪭㪣㪔㪋㩾㪿㪌
㪧㪚㪣㪢
㪣
㪭
㪠
㪛
㪚
㪧
㪟
㪭
㪠
㪛
㪚
㪧
㪧㪚㪣㪢㪛
㪟㪪㪰㪥㪚
Internal clock
Figure 44