Renesas Emulation Probe M306V8T-EPB - Manual (Page 68)

M306V8T-EPB User’s Manual 4. Hardware Specifications
REJ10J0777-0100 Rev.1.00 2005.08.01 Page 68 of 90
Figure 4.2 Memory expansion mode and microprocessor mode (2-wait, accessing external area, using multiplex bus)
Read timing
Write timing
BCLK
CSi
ADi
BHE
ALE
RD
ADi
/DBi
td(BCLK-CS) th(BCLK-CS)
tcyc
td(BCLK-AD) th(BCLK-AD)
th(RD-CS)
td(BCLK-ALE)
th(BCLK-ALE)
th(RD-AD)
td(BCLK-RD)
th(BCLK-RD)
tac3(RD-DB)
Hi-Z
tsu(DB-RD)
th(RD-DB)
BCLK
CSi
ADi
BHE
ALE
WR,
WRL ,WRH
ADi
/DBi
td(BCLK-CS) th(BCLK-CS)
tcyc
td(BCLK-AD)
td(BCLK-ALE)
th(BCLK-ALE)
th(WR-AD)
td(BCLK-WR) th(BCLK-WR)
td(BCLK-DB)
td(DB-WR)
th(BCLK-AD)
th(WR-CS)
th(WR-DB)
th(BCLK-DB)
td(AD-ALE) th(ALE-AD)
td(AD-RD)
tdz(RD-AD)
td(AD-ALE) th(ALE-AD)
td(AD-WR)