Avago Technologies LSI53C140 - Manual (Page 75)

LSI53C140 Ultra2 SCSI Bus Expander IX-1
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
Index
Numerics
160-pin plastic quad flat pack 1-7
160-pin PQFP 3-24
pin diagram 3-3
192-ball PBGA 3-26
ball diagram 3-4
192-ball plastic ball grid array 1-7
3-state 2-8
leakage 3-14
A
A_DIFFSENS 3-7
A_HVD_MODE 3-7
A_SACK 2-10
A_SACK+/- 3-7
A_SATN 2-11
A_SATN+/- 3-7
A_SBSY 2-9
A_SBSY+/- 3-7
A_SCD 2-11
A_SCD+/- 3-7
A_SD[15:0] 2-7
A_SD[15:0]+/- 3-7
A_SDP[1:0] 2-7
A_SDP[1:0]+/- 3-7
A_SIO 2-11
A_SIO+/- 3-7
A_SMSG 2-11
A_SMSG+/- 3-7
A_SREQ 2-10
A_SREQ+/- 3-7
A_SRST 2-9
A_SRST+/- 3-7
A_SSEL 2-8
A_SSEL+/- 3-7
absolute maximum stress ratings 3-11
AC characteristics 3-21
acknowledge 2-3
(SACK) 2-10
active negation 2-3
applications 1-3
attention (SATN) 2-11
B
B_DIFFSENS 3-8
B_HVD_MODE 3-8
B_SACK 2-10
B_SACK+/- 3-8
B_SATN 2-11
B_SATN+/- 3-8
B_SBSY 2-9
B_SBSY+/- 3-8
B_SCD 2-11
B_SCD+/- 3-8
B_SD[15:0] 2-7
B_SD[15:0]+/- 3-8
B_SDP[1:0] 2-7
B_SDP[1:0]+/- 3-8
B_SIO 2-11
B_SIO+/- 3-8
B_SMSG 2-11
B_SMSG+/- 3-8
B_SREQ 2-10
B_SREQ+/- 3-8
B_SRST 2-9
B_SRST+/- 3-8
B_SSEL 2-8
B_SSEL+/- 3-8
backward compatibility 1-8
balanced duty cycles 2-3
bidirectional
connections 2-2
SCSI Signals 3-15
SCSI signals 3-14
BSY_LED 2-8 , 3-9
bus timing 2-5
busy (BSY) 2-9
C
calibration 2-5
chip reset (RESET/) 2-13
CLOCK 3-9
clock
(CLOCK) 2-15
signal 2-8
timing 3-21
control/data (SCD) 2-11
D
data 2-3 , 2-7
DC characteristics 3-11
delay settings 2-5
differential transceivers 1-8
DIFFSENS 2-4 , 2-5
receiver 2-5
DIFFSENS SCSI Signals 3-14
direction control signal polarities 2-12
double clocking of data 2-3