Table 3.4 power and ground pins, Power and ground pins, Table 3.4 – Avago Technologies LSI53C140 User Manual
Page 44
3-10
LSI53C140 Specifications
Ver. 2.1
Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
lists and describes the LSI53C140 power and ground pins.
Table 3.4
Power and Ground Pins
Name
Pin
Ball
Type
Description
VDD
SCSI
10, 27, 37, 51, 66,
75, 81, 99, 113, 121,
133
C5, C9, C13, E3, E15,
J3, J15, N3, N15, R5,
R9, R13
I
Power supplies to the SCSI bus
I/O pins.
VDD
CORE
26, 98
B8, K3, K15, U8
I
Power supplies to the CORE
logic.
VDD
IO
158
A2
I
Power supplies to the I/O logic.
VSS
7, 15, 22, 32, 41,
48, 56, 63, 71, 72,
80, 88, 95, 102, 110,
120, 128, 136, 160,
23, 103, 144
C7, C11, G3, G7, G8,
G9, G10, G11, G15,
H7, H8, H9, H10, H11,
J7, J8, J10, J11, K7,
K8, K9, K10, K11, L3,
L7, L8, L9, L10, L11,
L15, R7, R11
I
Ground ring.
RBIAS
38
R1
I
Receiver bias control, R =
9.76 k
Ω
1%.
NC
151–156
A1, A4, A5, A17, B3,
B4, C4, C6, C14, C15,
D3, F3, F15, H15, K17,
L2, P15, R4, R10, R12,
T1, U1, U6, U16, U17
N/A
No Connections.
Notes:
•
All V
DD
pins must be supplied 3.3 V. The LSI53C140 output signals drive 3.3 V.
•
If the power supplies to the VDD
IO
and VDD
CORE
pins in a chip testing environment are separated,
either power up the pins simultaneously or power up VDD
CORE
before VDD
IO
. The VDD
IO
pin must
always power down before the VDD
CORE
pin.