Avago Technologies LSI53C140 - Manual (Page 31)

SCSI Signal Descriptions 2-13
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
For example, if a differential source is plugged into the B Side that has
been configured to run in the differential mode and if a SE source is
detected, then the B Side is disabled and no B Side signals are driven.
This is a protection mechanism for SE interfaces that are connected to
differential drivers.
2.2.11 Control Signals
This section provides information about RESET/, WS_ENABLE, and
XFER_ACTIVE pins. It also describes the function of the CLOCK input.
2.2.11.1 Chip Reset (RESET/)
This general purpose chip reset forces all of the internal elements of the
LSI53C140 into a known state. It brings the State Machine to an idle
state and forces all controls to a passive state. The minimum RESET/
input asserted pulse width is 100 ns.
The LSI53C140 also contains an internal Power On Reset (POR)
function that is ORed with the chip reset pin. This eliminates the need
for an external chip reset if the power supply meets ramp up
specifications.
Table 2.5 describes the RESET/ Control signal polarity.
Table 2.4 Mode Sense Control Voltage Levels
Voltage Mode
−
0.35 to +0.5 SE
+0.7 to +1.9 LVD
+2.4 to +5.5 HVD
Table 2.5 RESET/ Control Signal Polarity
Signal Level State Effect
LOW = 0 Asserted The chip forces reset to all internal LSI53C140
elements.
HIGH = 1 Deasserted LSI53C140 is not in a forced reset state.