Avago Technologies LSI53C140 - Manual (Page 17)

Benefits of LVDlink 1-7
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
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Accepts any asynchronous or synchronous transfer speed up to
Ultra2 SCSI (for LVD to LVD mode only)
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Dynamic addition/removal of SCSI bus segments by using the
electrical isolation mode
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Does not consume a SCSI ID
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Propagates the RESET/ signal from one side to the other regardless
of the SCSI bus state
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Notifies initiator(s) of changes in transmission mode (SE/LVD/HVD)
on A or B side segments by using SCSI bus RESET/
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SCSI Busy LED driver for activity indicator
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Up to four LSI53C140s may be cascaded
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Does not require software
1.2.2 Specifications
The LSI53C140 specifications are:
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40 MHz Input Clock
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160-pin PQFP
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192-ball PBGA; This package is a drop in replacement for the
LSI53C180 when the design uses the LSI53C180 pinout.
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Compliant with the SCSI Parallel Interface (SPI-2)
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Compliant with SCSI Enhanced Parallel Interface (EPI)
Specifications
1.3 Benefits of LVDlink
The LSI53C140 supports LVD technology for SCSI, a signaling
technology that increases the reliability of SCSI data transfers over
longer distances than those supported by SE SCSI technology. The low
current output of LVD allows the I/O transceivers to be integrated directly
onto the chip. LVD provides the reliability of HVD SCSI technology
without the added cost of external differential transceivers. LVD allows a
longer SCSI cable and more devices on the bus. LVD provides a
long-term migration path to even faster SCSI transfer rates without
compromising signal integrity, cable length, or connectivity.