Avago Technologies LSI53C140 - Manual (Page 23)

Interface Signal Descriptions 2-5
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
2.1.3 Precision Delay Control
The Precision Delay Control block provides calibration information to the
precision delay elements in the retiming logic block in order to maintain
precise timing as signals propagate through the device. As the
LSI53C140 operating conditions (such as voltage and temperature) vary
over time, the Precision Delay Control block periodically updates the
delay settings in the retiming logic to maintain constant and precise
control over bus timing.
2.1.4 State Machine Control
The State Machine Control keeps track of the SCSI bus phase protocol
and other internal operating conditions. This block provides signals to the
retiming logic that identify how to properly handle SCSI bus signal
retiming and protocol, based on observed bus conditions.
2.1.5 DIFFSENS Receiver
The LSI53C140 contains LVD DIFFSENS receivers that detect the
voltage level on the A Side or B Side DIFFSENS lines to inform the
LSI53C140 of the transmission mode being used by the SCSI buses. The
LVD DIFFSENS receivers are capable of detecting the voltage level of
incoming SCSI signals to determine whether it is from an SE, LVD, or
HVD device. A device does not change its present signal driver or
receiver mode based on the DIFFSENS voltage levels unless a new
mode is sensed continuously for at least 100 ms.
Transmission mode detection for SE, LVD, or HVD is accomplished
through the use of the DIFFSENS lines.
Table 2.1 shows the voltages on
the DIFFSENS lines and modes they will cause.
Table 2.1 DIFFSENS Voltage Levels
Voltage Mode
−
0.35 to +0.5 SE
+0.7 to +1.9 LVD
+2.4 to +5.5 HVD