Avago Technologies LSI53C140 - Manual (Page 42)

3-8 LSI53C140 Specifications
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
Table 3.2 lists and describes the SCSI B side interface pins for the
LSI53C140.
Table 3.2 SCSI B Side Interface Pins
Name Pin Ball Type Description
B_SSEL+,
−
18, 19 H2, J1 I/O B Side SCSI bus Select control signal.
B_SBSY+,
−
30, 31 M3, N1 I/O B Side SCSI bus Busy control signal.
B_SRST+,
−
24, 25 K2, L1 I/O B Side SCSI bus Reset control signal.
B_SREQ+,
−
13, 14 G1, G2 I/O B Side SCSI bus Request control signal.
B_SACK+,
−
28, 29 M1, M2 I/O B Side SCSI bus Acknowledge control
signal.
B_SMSG+,
−
20, 21 J2, K1 I/O B Side SCSI bus Message control
signal.
B_SCD+,
−
16, 17 H3, H1 I/O B Side SCSI bus Control and Data
control signal.
B_SIO+,
−
11, 12 F1, F2 I/O B Side SCSI bus Input and Output
control signal.
B_SATN+,
−
33, 34 N2, P1 I/O B Side SCSI bus Attention control signal.
B_SDP[1:0]+,
−
59, 60, 35, 36 T9, U9, P3, P2 I/O B Side SCSI bus Data Parity signal.
B_SD[15:0]+,
−
61, 62, 64, 65,
67, 68, 69, 70,
1, 2, 3, 4, 5, 6,
8, 9, 39, 40,
42, 43, 44, 45,
46, 47, 49, 50,
52, 53, 54, 55,
57, 58 T10, U10, T11,
U11, T12, U12,
T13, U13, B1,
B2, C1, C2,
D1, D2, E1, E2,
R2, R3, T2, U2,
T3, U3, T4, U4,
T5, U5, R6, T6,
T7, U7, T8, R8 I/O B Side SCSI bus Data signals.
B_DIFFSENS 159 C3 I B Side SCSI bus Differential Sense
signal.
B_HVD_MODE 157 A3 I B Side SCSI bus HVD Mode control
signal.