Avago Technologies LSI53C140 - Manual (Page 67)

LSI53C140 Ultra2 SCSI Bus Expander B-1
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
Appendix B
Board Design
Considerations
This appenidx describes the design considerations for using the
LSI53C180 as a drop in replacement for the LSI53C140. Both chips are
available as a 192-ball PBGA in a 23 x 23 mm package. This appendix
also describes the differences in pin configurations required for operation
of the two devices.
The LSI53C180 supports Ultra160 data transfer rates for an LVD bus and
Ultra data transfer rates for an SE bus. The LSI53C180 does not support
HVD. Thus, HVD mode enable pins for each port are no longer present.
In the LSI53C140, pins B7 and A3 should be pulled to GND to disable
HVD mode when operating in SE or LVD mode. These two pins are no
connects in the LSI53C180.
The LSI53C180 has an independent RBIAS pin to control margining for
each bus, rather than a single pin for both buses as implemented in the
LSI53C140. A 10 k
Ω
pull-up resistor on RBIAS is recommended to
provide the correct margining. If initially designing for the LSI53C140 with
the intention of upgrading to the LSI53C180 at a later time, a footprint
from the pull-up resistor for the A-RBIAS signal should be implemented.
Table B.1 summarizes the information in the previous paragraphs.
Table B.1 Pin Adjustments
Pin
Number LSI53C140 Signal
LSI53C180 Signal
K17 NC A-RBIAS
B7 A_HVD_MODE NC
A3 B_HVD_MODE NC