Avago Technologies LSI53C140 - Manual (Page 20)

2-2 Functional Descriptions
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
Figure 2.1 LSI53C140 Block Diagram
In its simplest form, the LSI53C140 passes data and parity from a source
bus to a load bus. The side asserting, deasserting, or releasing the SCSI
signals is the source side. This model of the LSI53C140 represents
pieces of wire that allow corresponding SCSI signals to flow from one
side to the other side. The LSI53C140 monitors arbitration and selection
by devices on the bus so it can enable the proper drivers to pass the
signals along. In addition, the LSI53C140 does signal retiming to
maintain the signal skew budget from the source bus to the load bus.
2.1.1 SCSI A Side and B Side Control Blocks
The SCSI A Side pins are connected internally to the corresponding
SCSI B Side pins, forming bidirectional connections to the SCSI bus.
In the LVD/LVD mode, the SCSI A Side and B Side control blocks
connect to both targets and initiators and accept any asynchronous or
synchronous data transfer rates up to the 80 Mbytes/s rate of Wide
Ultra2 SCSI. TolerANT
®
and LVDlink technologies are part of both the A
Side and B Side control blocks.
Retiming
Logic
Precision
Delay
Control
State
Machine
Control
LV
D
DIFFSENS
Receiv
er
LVD
DIFFSENS
Receiv
er
SCSI Contr
ol Bloc
k
SCSI Contr
ol Bloc
k
LVDink T
ransceiv
ers
LVDink T
ransceiv
e
rs
Control
Signals
LVD, SE, HVD
Wide Ultra SCSI Bus
(A Side)
LVD, SE, HVD
Wide Ultra SCSI Bus
(B Side)
A_DIFFSENS B_DIFFSENS
40 MHz Clock Input