Avago Technologies LSI53C140 - Manual (Page 41)

General Description 3-7
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
Table 3.1 lists and describes the SCSI A side interface pins for the
LSI53C140.
Table 3.1 SCSI A Side Interface Pins
Name Pin Ball Type Description
A_SSEL+,
−
91, 92 M15, M16 I/O A Side SCSI bus Select control signal.
A_SBSY+,
−
104, 105 H16, H17 I/O A Side SCSI bus Busy control signal.
A_SRST+,
−
96, 97 L17, K16 I/O A Side SCSI bus Reset control signal.
A_SREQ+,
−
86, 87 P16, P17 I/O A Side SCSI bus Request control
signal.
A_SACK+,
−
100, 101 J16, J17 I/O A Side SCSI bus Acknowledge control
signal.
A_SMSG+,
−
93, 94 M17, L16 I/O A Side SCSI bus Message control
signal.
A_SCD+,
−
89, 90 N16, N17 I/O A Side SCSI bus Control and Data
control signal.
A_SIO+,
−
84, 85 R16, R17 I/O A Side SCSI bus Input and Output
control signal.
A_SATN+,
−
106, 107 G16, G17 I/O A Side SCSI bus Attention control
signal.
A_SDP[1:0]+,
−
131, 132, 108,
109 C12, B12, F16,
F17 I/O A Side SCSI bus Data Parity signal.
A_SD[15:0]+,
−
134, 135, 137,
138, 139, 140
141, 142,
73, 74, 76, 77,
78, 79, 82, 83,
111, 112, 114,
115, 116, 117,
118, 119, 122,
123, 124, 125,
126, 127, 129,
130 A12, B11, A11,
B10, C10, A10,
B9, A9, T14,
U14, R14, T15,
U15, R15, T16,
T17, E16, E17,
D16, D17, D15,
C16, C17, B17,
B16, A16, B15,
A15, B14, A14,
B13, A13 I/O A Side SCSI bus Data signals.
A_DIFFSENS 143 A8 I A Side SCSI bus Differential Sense
signal.
A_HVD_MODE 145 B7 I A Side SCSI bus HVD Mode control
signal.